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gsm850/900/1800/1900 single chip gsm radio AD6548/9 rev b (1 st october 2007) information furnished by mediatek is believed to be accurate and reliable. however, no responsibility is assumed by mediatek for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is gr anted by implication or ot herwise under any patent or patent rights of mediatek. trademar ks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.mediatek.com fax: 781/326-8703 ? 2008 mediatek, inc. all rights reserved. features fully integrated gsm transceiver including direct conversion receiver 4 differential lnas integrated active rx channel select filters programmable gain baseband amplifiers translation loop direct vco modulator integrated tx vco and tank external tx filters eliminated integrated loop filter components high performance multi band pll system fast fractional-n synthesizer integrated local oscillator vco fully integrated loop filters crystal reference oscillator & tuning system (AD6548) power management integrated ldos allow direct battery supply connection small footprint 32-lead 5 x 5 mm chipscale package applications dual, triple and quad band radios - gsm850, e-gsm 900, dcs1800 and pcs1900 - gprs to class 12- edge rx AD6548/9 lfcsp-32 (5x5 mm) 1 2 9 3 4 5 6 7 8 24 23 22 21 20 19 18 23 17 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 vcc_fe i ib vcc_bbi sdata sclk sen nc txop_lo vldo3 txop_hi vcc_txvco vdd vbat vldo1 vldo2 vcc_ref vafc refinb refin ref_op qb q vcc_bbq rx1900b rx1900 rx1800b rx1800 rx900b rx900 rx850b rx850 general description the AD6548/9 provides a highly integrated direct conversion radio solution that combines, on a single chip, all radio and power management functions nece ssary to build the most com- pact gsm radio solution possible. the only external components required for a complete radio design are the rx saws, pa, switchplexer and a few passives enabling an extremely small cost effective gsm radio solution. the AD6548/9 uses the industry proven direct conversion re- ceiver architecture of the othello tm family. for quad band appli- cations the front end features four fully integrated programmable gain differential lnas. the rf is then downconverted by quad- rature mixers and then fed to the baseband programmable-gain amplifiers and active filters for channel selection. the receiver output pins can be directly connected to the baseband analog processor. the receive path features automatic calibration and tracking to remove dc offsets. the transmitter features a translation-loop architecture for di- rectly modulating baseband signals onto the integrated tx vco. the translation-loop modulator and tx vco are extremely low noise removing the need for external saw filters prior to the pa. the AD6548/9 uses a single integrated lo vco for both the receive and the transmit circuits. the synthesizer lock times are optimized for gprs applications up to and including class 12. to dramatically reduce the bom both tx translational loop and main pll loop filters are fully integrated into the device. AD6548 incorporates a complete reference crystal calibration system. this allows the external vctcxo to be replaced with a low cost crystal. no other exte rnal components are required. the ad6549 uses the traditional vctcxo reference source. the AD6548/9 also contains on-chip low dropout voltage regula- tors (ldos) to deliver regulated supply voltages to the functions on chip, with a battery input voltage of between 2.9v and 5.5v. comprehensive power down options are included to minimize power consumption in normal use. a standard 3 wire serial interface is used to program the ic. the interface features low-voltage digital interface buffers compatible with logic levels from 1.6v to 3.0v. the AD6548/9 is packaged in a 5mm 5mm , 32-lead lfcsp package. ordering guide model temperature range package AD6548bcpz -20c to +85c lfcsp-32 ad6549bcpz -20c to +85c lfcsp-32 www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pa tents or other rights of third parties, which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of meditek. mediatek proprietary information -2- rev b antenna switch module dc offset correction dc offset correction pfd /2 ldo reg 3 ldo reg 2 ldo reg 1 frac-n synth rx lo generator tx lo generator xtal osc + tuning serial interface /4 sen sclk sdata rx1900b rx1900 rx1800b rx1800 rx900b rx900 rx850b rx850 txop_hi txop_lo vdd vbat vldo3 vldo2 vldo1 lo vco supply ref_op refin refinb vafc vcc_ref q qb i ib vcc_bbi vcc_bbq lna gain reduction tx_lo2 tx_lo1 tx_lo2 tx_lo1 general supply tx circuits supply clk rxqb rxq txqb txq rxib rxi txi txib afc ref_op band control tx loop filter gsm1800/1900 gsm850/900 pa module AD6548 vcc_fe vcc_txvco ref supply vcc_ txvco figure 1 AD6548 & ad6549 block diagrams antenna switch module dc offset correction dc offset correction pfd /2 ldo reg 3 ldo reg 2 ldo reg 1 frac-n synth rx lo generator tx lo generator serial interface /4 sen sclk sdata rx1900b rx1900 rx1800b rx1800 rx900b rx900 rx850b rx850 txop_hi txop_lo vdd vbat vldo1 vldo2 vldo3 lo vco supply ref_op refinb vcc_ref q qb i ib vcc_bbi vcc_bbq lna gain reduction tx_lo2 tx_lo1 tx_lo2 tx_lo1 general supply tx circuits supply clk rxqb rxq txqb txq rxib rxi txi txib afc ref_op band control tx loop filter gsm1800/1900 gsm850/900 pa module ad6549 vcc_fe vcc_txvco ref supply vctcxo vcc_ txvco www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pa tents or other rights of third parties, which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of mediatek. rev b -3- mediatek proprietary information table of contents general description .............................................. 1 functional des criptio n ....................................... 4 receiver ............................................................................ 4 low noise am plifiers ................................................... 4 down-converting mixe rs.............................................. 4 baseband amplifiers / low pass filters........................ 4 baseband output d.c. offset correction ...................... 5 receiver local oscillato r (lo) gene rator ................... 5 transmitter ....................................................................... 5 overview ....................................................................... 5 quadrature modulat or ................................................... 6 phase frequency detector (pfd) .................................. 6 loop filte r...................................................................... 6 tx vco ........................................................................ 6 feedback down-conve rting mixer ............................... 6 transmit frequency plan............................................... 6 main frequency synthesizer ........................................... 6 fractional n dividers .................................................... 6 phase frequency detector/charge pump....................... 6 synthesizer l oop filter .................................................. 7 voltage controlle d oscillator........................................ 7 reference os cillator ...................................................... 7 power management.......................................................... 7 overview ....................................................................... 7 ldo usage.................................................................... 7 serial interface................................................................. 8 overview ....................................................................... 8 serial word format ....................................................... 8 programming pr ocedure s .................................. 8 synthesiser programming................................................ 8 transmit example.......................................................... 9 receive example ........................................................... 9 modes of operation.......................................................... 9 control se quence......................................................... 10 calibration desc ription.................................................. 12 register defi nitions............................................. 13 register a ddresses ...................................................... 13 register map ............................................................... 13 specifications ........................................................... 15 operating co nditions ..................................................... 15 absolute max imum ratin gs........................................... 15 general + re gulato rs ..................................................... 16 supply cu rrent ............................................................ 16 regulator s.................................................................... 16 receive sections ............................................................. 17 gsm850 and e-gsm 900 receiver ............................ 17 gsm1800 and gsm 1900 receive rs............................ 18 baseband amp lifiers ................................................... 19 baseband f ilters .......................................................... 19 transmit section ............................................................ 20 transmitter .................................................................. 20 txop_lo output 1 ....................................................... 20 txop_hi output 1 ........................................................ 20 tx baseband i/ q input s............................................... 20 fractional-n sy nthesizer ............................................... 21 synthesizer .................................................................. 21 lock time ................................................................... 21 reference os cillator....................................................... 22 AD6548 crystal oscillator 1 ......................................... 22 ad6549 input refere nce buffer ................................. 22 AD6548/9 reference out put ....................................... 22 serial port....................................................................... 23 serial in terface ............................................................ 23 timing cond itions....................................................... 23 package dimensions .............................................. 26 change list................................................................. 26 www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pate nts or other rights of third pa rties, which may result from its use. no license is granted by implication or otherwise under an y patent or patent rights of meditek. mediatek proprietary information -4- rev b table 1. AD6548/9 pin descriptions no name description no name description 1 vcc_fe front end supply (ip) 3 17 vcc_ref reference oscillator supply (ip) 2 i i baseband input/output 18 vafc AD6548 crystal freq control (ip) ad6549: connect to vcc_ref 3 ib i baseband input/output 19 refi nb crystal / vctcxo connection 4 vcc_bbi baseband i, tx path supply (ip) 3 20 refin crystal connection 5 sdata serial port data 21 ref_op reference frequency output 6 sclk serial port clock 22 qb q baseband input/output 7 sen serial port enable 23 q q baseband input/output 8 n/c not connected 24 vcc_ bbq baseband q supply (ip) 3 9 vldo3 tx ldo output 1 25 rx1900b pcs 1900 lna input 10 txop_lo transmit o/p (850/900mhz) 26 rx1900 pcs 1900 lna input 11 txop_hi transmit o/p (1800/1900mhz) 27 rx1800b dcs 1800 lna input 12 vcc_txvco tx vco supply (1) 28 rx1800 dcs 1800 lna input 13 vdd serial interface supply 29 rx900b e-gsm 900 lna input 14 vbat battery i/p for ldo reg?s 30 rx900 e-gsm 900 lna input 15 vldo1 ldo regulator output 2 31 rx850b gsm 850 lna input 16 vldo2 lo vco supply 1 32 rx850 gsm 850 lna input notes: 1. ldo output pin is for external decoupling only. do not connect to any other supply. 2. internally connected to synth supply (counters + sdm + charge pump) 3. these supply pins should only be connected to the regulated supply provided by vldo1; not to any other supply. functional description receiver 90 o rx1900b rx1900 rx1800b rx1800 rx900b rx900 rx850b rx850 90 o hi band divider low band divider q channel i channel low band quadrature mixer high band quadrature mixer figure 2 receiver chain the AD6548/9 receiver section fully integrates all the rf and baseband signal processing. each major block is described in the following sections. low noise amplifiers the AD6548/9 includes four fully integrated low noise am- plifiers (lnas), to support qua d band applications without further external active component s. the lnas have differential inputs which minimize the effect of unwanted interferers. the inputs are easily matched to i ndustry standard front end mod- ules (fems) or discrete rx saw filters. the outputs of the lnas are directly coupled to the down-converting mixers. the voltage gain of the lnas are typically 24 db. each lna can be switch to a low gain mode when receiving large input sig- nals as part of the agc system. down-converting mixers two quadrature mixers are used to mix down the signals from the lnas, one for the high bands (1800 and 1900 mhz) and one for the low bands (850 and 900 mhz). the outputs of the mixers are connected to the baseband section through an inte- grated single pole filter with nominal cut-off frequency of 800khz. this acts as a ?roofing filter? for the largest blocking signals (i.e. those 3mhz) and prevents the baseband amplifi- ers from being overloaded. baseband amplifiers / low pass filters the baseband amplifiers provide the majority of the analog receiver gain. the filtering is provided by an integrated 5 th order chebyshev filter giving the necessary adjacent channel and blocking filtering, it is also acting as an anti-alias filtering for baseband ic?s converters. a final low pass pole is possible www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pate nts or other rights of third pa rties, which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of mediatek. rev b -5- mediatek proprietary information at each of the baseband outputs via internal series resistor along with an external shunt capacitor. the external capacitor is not normally required with adi baseband ics. the on chip filter has an auto calibration feature ensuring that the filters are tuned for optimum performance. the baseband amplifiers have programmable gain for system agc. a total of 57 db of gain control is provided in 3db steps programmable over the serial interface. this together with the lna gain control gives a total of 77db of gain control range. the receive baseband outputs are routed to the common rx/tx i/q ports for connection with the baseband converters. automatic tuning control gain control gain[4:0] i q ref optional figure 3 baseband amplifiers baseband output d.c. offset correction in order to minimize d.c. offsets inherent in the receiver and maximize dynamic range a d.c offset correction circuit is inte- grated. this correction is triggered over the serial bus and then an offset tracking loop is enabled to minimize residual offsets under all conditions. the tracking loop is fully hardware inte- grated, requiring no software intervention. receiver local oscilla tor (lo) generator the rx lo generator is used to avoid dc offset problems as- sociated with lo leakage into the receiver rf path. by operat- ing the vco at a frequency other than the desired receive fre- quencies, any leakage of the vco will fall out of band. the lo generator is used to convert th e offset synthesized vco output to the on-frequency quadrature lo required by the chipset. the lo generator is implemented as a regenerative frequency di- vider, performing a 2/3 multiplication of the vco output for the high band (dcs1800/pcs1900) and a 1/3 multiplication for low band (e-gsm 900/gsm850). transmitter /2 pfd regenerative divider 5/7 /2 850/900 mhz tx tx vco 1648-1910 mhz loop filter phase frequency detector main vco 2520-2985 mhz i q feedback down converting mixer /4 fractional-n synthesizer pfd band select switch 26 mhz reference 1800/1900 mhz tx figure 4 transmit path overview the transmit section of the AD6548/9 radio implements a translation loop modulator. this consists of a quadrature modu- lator, high speed phase-frequency detector (pfd) with charge pump output, loop filter, tx vco and a feedback down con- verting mixer. the vco output (divided by 2 for low band) is fed to the power amplifier with a portion internally fed back into the down-converting feedback mixer to close the feedback loop. www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pate nts or other rights of third pa rties, which may result from its use. no license is granted by implication or otherwise under an y patent or patent rights of meditek. mediatek proprietary information -6- rev b quadrature modulator the quadrature modulator take s the baseband i & q signals and translates these into a gmsk signal at the transmit inter- mediate frequency (tx if). after bandpass filtering and limit- ing the tx if signal is used as the reference input to the phase frequency detector (pfd) of the transmit pll. phase frequency detector (pfd) the pfd ensures that the transmitted signal contains the re- quired modulation and is accurately locked to the desired gsm channel. the downconverted feedback signal from the tx vco and the quadrature modulator output are phase compared by the pfd. the pfd charge pump generates a current pulse proportional to the difference in phase which is applied to the loop filter. loop filter to minimize complexity of the external pcb layout the tx loop filter is fully integrated in to the ic. at power up the filter is automatically calibrated as part of the baseband filter cal, eliminating process tolerances. the calibration is fully inte- grated and requires no extra programming. tx vco the transmit voltage controlled oscillator (tx vco) and tank components are a fully integr ated subsystem. the subsys- tem includes pa drivers so the outputs are used to directly drive the external pas. the low noise oscillator design and internal filtering mean that ex ternal tx saw filters are not required. in low band operation the tx vco output is divided by two and filtered. the tx vco is automatically calibrated to ensure optimum performance ove r its operating frequency of 1648 to 1910 mhz. feedback down-converting mixer the feedback down converting mixer is used to translate the tx vco output frequency to the tx if. an integrated band pass filter exists between the mixer and the pfd to filter the mixers unwanted side band a nd higher order mixing products. transmit frequency plan unlike many other translation loop modulators the AD6548/9 uses only a single vco source to derive the local oscillator signal for both the feedback down-converting mixer and the quadrature modulator. therefore there is a fixed relationship between the tx if frequency and the lo vco frequency such that: f if = f vco x 5 28 this ratio was chosen to minimize vco tuning range, tx if frequency variation and ensure ex cellent transmit spectral mask performance. the feedback-down converting mixer operates low side in- jection for the high bands and high side injection for the low bands. the final relationship between the transmitted tx fre- quency and the lo vco frequency is different between the two bands. specifically: f vco = f tx_lowband x 28 9 f vco = f tx_hiband x 28 19 these relationships are taken account of in the synthesizer architecture and programming. main frequency synthesizer the AD6548/9 has a single fast-l ocking fractional synthesizer used for vco control in both receive and transmit mode. the entire system including vco, tank, fractional n dividers, sigma delta compensation, charge pump and loop filters are fully integrated. the only extern al component is the frequency reference. the synthesizer is controlled via the serial interface. the vco is fed into the respective dividers to generate the appropriate lo frequencies for the rx and tx bands. fractional n dividers the fractional n divider allows the pll system to have a smaller step size than the comparison frequency which is set by the external reference to 26 mhz. this feature allows all the gsm frequency band rasters to be achieved, with fast lock times and good phase noise characteristics. the divider section consists of a dual modulus 8/9 prescaler, integer m & a dividers, and fractional n system based on sigma-delta modulation to genera te the required fractional di- vide ratio. the denominator of the fractional divider can be set to 3 different values, (1040, 1170, 1235), depending on the mode of operation. for example a denominator of 1040 with an input fraction f maintains an average value of f/1040 allowing 25 khz steps when operated at a reference of 26 mhz. the overall count value is thus: 8*m + a + fraction where: m is 4 bits, but the msb is set to 1 a is 3 bits fraction is n/ denominator. the denominator is set to one of 3 values: 1040, 1170, 1235. n is a 11 bit value. values for m, a and n are loaded from serial interface word, but the denominator is automatically set according to the mode. refer to the programming procedures for more details. phase frequency detector/charge pump a phase frequency detector (pfd) is used for the pll phase detector. the charge pump is designed such that good matching of up and down currents is achie ved over a wide output operat- ing range. the charge pump output is internally routed to the integrated synthesizer loop filter. www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pate nts or other rights of third pa rties, which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of mediatek. rev b -7- mediatek proprietary information synthesizer loop filter to minimize complexity of the external pcb layout the main synthesizer loop filter is also fully integrated into the ic. no external components or adjustments are required . voltage controlled oscillator the integrated voltage contro lled oscillator (vco) is a com- plete self-calibrating subsystem. this employs a fully auto- mated digital self-calibration f unction to ensure optimum phase noise performance over the entire frequency range. the vco generates frequencies betw een 2520mhz and 2985mhz as required to operate in the four gsm bands for rx and tx. reference oscillator the reference input circuitry is different between the AD6548 and ad6549 as described in the table. chip number source ad6549 vctcxo AD6548 crystal ad6549 description: the 26mhz reference frequency is provided by an external vctcxo module, supplied to the refinb pin. the refin pin must be ac grounded via a 1nf capacitor. in this case tem- perature and frequency stability are provided by the vctcxo module. ref_op [21] [18] refinb[19] vcc_ref [17] 26 mhz 600 mv 1n 2.75v refin[20] vctcxo afc_rf ad6549 figure 5 ad6549 simplified reference connections AD6548 description: the AD6548 requires only an external low cost crystal as the frequency reference. the circuitry to oscillate the crystal and tune its frequency is fully integrated. for good noise immunity the oscillator is a balanced implementation requiring the crystal to be connected across 2 pins. there is a programmable capaci- tor array included for coarse tuning of fixed offsets (e.g. crystal manufacturing tolerance), and an integrated varactor for dy- namic control. the oscillator is designed for use with a 26mhz crystal. the crystal is connected as shown in figure 6. dedicated control software ensures excellent frequency stabil- ity under all circumstances. both AD6548 and ad6549 reference oscillators provides a 26 mhz 600mvpp (typical) output (ref_op), for use as the baseband clock input. this is designed for low harmonic con- tent. 2.75v ref_op [21] vafc [18] refinb[19] vcc_ref [17] refin[20] baseband afc control 26 mhz xtal 26 mhz 600 mv 1n AD6548 figure 6 AD6548 crystal oscillator external connections. power management overview for direct battery supply connect, and to reduce external cir- cuitry complexity the AD6548/9 features three low drop out regulators (ldos). the three ldos provide isolation of the oscillators and sensitive circu its from unwanted power supply and cross coupled noise. they also ensure the ic operation is robust over a wide range of power supply voltages. for power management the ldos are inde pendently controlled via the 3 wire serial bus. ldo usage the following table describes the ldo usage: ldo1 ldo2 ldo3 rx and tx baseband sections main vco tx vco table 2 : intended ldo use the ldo outputs require external connection to the respective pins described in table 3, and each requires decoupling capaci- tors. the ldos are designed to be unconditionally stable re- gardless of the capacitor?s esr. ldo op external connection vldo1 vcc_fe, vcc_bbi, vcc_bbq vldo2 no external connec tions, except for decoupling vldo3 no external connec tions, except for decoupling table 3 : ldo connections ldo1 derives its input referen ces from the crystal supply volt- age (vcc_ref). it is therefore expected that vcc_ref be supplied from a external ldo of nominal supply voltage 2.75v (e.g. adp3330 or analog baseband ic: vout=2.75v 1.4%). www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pate nts or other rights of third pa rties, which may result from its use. no license is granted by implication or otherwise under an y patent or patent rights of meditek. mediatek proprietary information -8- rev b serial interface overview a standard 3 wire bus is used to communicate with the device as shown in figure 7. the seri al bus is a common bus which can be shared with other rf and baseband devices. // // // msb a0 sdata sen sclk data latched figure 7 serial interface bus data is clocked in on the rising edge of sclk with msb first. sdata is latched on the rising edge of sen. if immediate action is required this is aligned with rising edge of sen. if this is not required the word is latched for later use. serial word format sdata is clocked through a set of flip-flops, the last 5 defin- ing the address field. the addre ss decoder runs all the time but sdata is only latched on the rising edge of sen. preceding the address field is a 2 bit opcode field defining the action (ta- ble 4). the remaining bits are for data to program register con- tents. the length of the data field varies depending on the specified register. refer to the register definition section for details on register content, and the specification section for details on the hardware timing parameters. dn d7 d6 d5 d4 d3 d2 d1 d0 a0a1a2a3a4 5 bit address field op0 op1 2 bit op code field lsb msb variable length data field first bit transmitted last bit transmitted figure 8 serial word format. op0 op1 operation description 0 0 write normal register write 0 1 clear clear register with supplied mask 1 0 set set register with supplied mask 1 1 reserved do no use table 4 op code definition the data length on the serial bus can be adjusted to accommo- date different word lengths needed in different situations. the maximum data word length in normal operation is 17, giving a total maximum length (dn) of 24 bits. programming procedures synthesiser programming the following section provides the method for deriving the AD6548/9 lo synthesizer programming words for receive and transmit modes. worked examples are then provided for extra clarity. calculation of nint and nfrac: 1) calculate the channel frequency from the mode and arfcn number provide by the protocol stack. this is achieved using the frequency tables provided in 3gpp ts 45.005. this frequency is labelled rf in step 2. 2) calculate AD6548/9 lo freque ncy from the rf frequency and mode: receive mode: lo = 3*rf .............. (gsm850/e- gsm 900) lo = (3/2)*rf .........( dcs1800/pcs1900) transmit mode: lo = (28/9)*rf .......(gsm850/e-gsm 900) lo = (28/19)*rf ?.(dcs1800/pcs1900) 3) calculate neff (effective value of the divider) for 26mhz reference. neff=lo / 26 (lo in mhz) 4) neff must be expressed as in teger and a fractional parts: nint + (nfrac/mod) = neff nint is an integer nfrac is the fractional portion. mod is the sigma delta modulus. the modulus (mod) is auto matically selected de- pending on the tx/rx mode select and the band se- lect according to the table below: mode band mod rx - 1040 tx e-gsm900 1170 tx dcs1800 1235 tx pcs1900 1235 tx gsm850 1170 5) program register 6. use the binary equivalents of nint and nfrac to program register 6. note : the msb of nint (which should always be ?1?) is dropped as this bit is hard coded internal to the ic. www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pate nts or other rights of third pa rties, which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of mediatek. rev b -9- mediatek proprietary information transmit example arfcn=124, e-gsm 900, mode tx: carrier frequency = 914.8 mhz (step 1) lo = 2846.04444? mhz (step 2) neff = 109.4632479.. (step 3) mod=1170 (step 4) nint = integer part of neff = 109 [b1101101] nfrac =1170*0.4632479.. = 542 [b01000011110] combine binary nint & nfrac [remember to drop nint msb] register 6 content lsb nfrac nint 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 0 1 1 1 1 0 1 0 1 1 0 1 receive example arfcn=846, dcs1800, mode rx: carrier frequency = 1872.0 mhz (step 1) lo = 2808.0 mhz (step 2) neff = 108.00 (step 3) mod = 1040 (step 4) nint = integer part of neff = 108 [b1101100] nfrac =1040*0 = 0 [b00000000000] combine binary nint & nfrac [remember to drop nint msb] register 6 content lsb nfrac nint 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 modes of operation the AD6548/9 can be configured into many different states, however the six most commonly applied to a gsm handset are described in this section. th e modes are determined by the vcc_ref and v dd power supplies provided and by serial bus programming. the v dd logic supply and vcc_ref supply for the reference supply and vctcxo (if present) are external ? either from the baseband or a separate regulator. off mode in off mode everything is powered down and only leakage current is drawn. all register contents & previous calibration results are lost. this mode is used when the handset is off. states: v dd is not present vcc_ref is not present ldos & all power bits disabled power down mode in power down mode everything is powered down, but the logic supply is present to maintain calibration settings and reg- ister contents. only leakage curre nt is drawn. this mode is used between paging blocks. states: v dd is present vcc_ref is not present ldos & all power bits disabled wait mode transitioning between power down and wait mode is simply controlled by the reference power supply (vcc_ref). the reference oscillator will automatically start when power is applied. this mode is used when the baseband section is transferring from sleep to fully operational before a receive or transmit burst. it can also be used if power down mode is not desired between paging blocks. minimu m current consumption is drawn. states: v dd is present vcc_ref is present ldos & all power bits disabled alert mode in alert mode the reference oscillator and synthesizer are active. this mode is present prior to a receive or transmit burst. ldo1 & ldo2 are enabled, but the rx_on and tx_on bits are clear in the power control register. states: v dd is present vcc_ref is present ldo1 & ldo2 enabled synth & lovco enabled receive mode in this mode the receiver is ac tive, so the radio will receive a gsm burst, after a short period has elapsed for the circuits to stabilize. it is the same as alert mode but with the receive sec- tion enabled via the serial interface. states: v dd is present vcc_ref is present ldo1 & ldo2 enabled synth & lovco enabled rx_on bit set transmit mode in this mode the transmitter is active, so the radio will transmit a gsm burst, after a short period has elapsed for the circuits to stabilize. it is the same as al ert mode but with the transmitter section enabled via the serial interface states: v dd is present vcc_ref is present ldo1 & ldo2 enabled synth & lovco enabled tx_on bit set (ldo3 automatically enabled) www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pate nts or other rights of third pa rties, which may result from its use. no license is granted by implication or otherwise under an y patent or patent rights of meditek. mediatek proprietary information -10- rev b control sequence initially the handset is in power down mode. only a very sim- ple timer chain in the baseband is running supplied by a 32 khz clock. AD6548/9 will only consume leakage current. after a set amount of time the baseband ic will enable vcc_ref and the reference oscillator will begi n to oscillator at 26 mhz. AD6548/9 will now be in wait mode. once the reference oscillator is stabilized the microprocessor will start. it will then set the AD6548/9 into alert mode and program the synthesiz- ers. just prior to the start of the receive burst the AD6548/9 will be set into receive mode until the burst ends where it will change back to alert mode and eventually all the way back to power down mode. the same principle applies to when a burst is transmitted where AD6548/9 changes from alert mode to transmit mode when the burst starts and back from trans- mit mode to alert mode when the burst ends. the typical tim- ing of the power up sequence prior to the rx or tx burst and the resulting current consumption are shown in figures 7 and 8. note that tx vco ldo is automatically enabled when tx is enabled. the ldo?s may be disabled in the inactive periods between bursts, however in the cases of gprs and hscsd ldo1 and ldo2 should be left enabled. the ldos alone draw minimal current. figure 9 typical timing of the power up sequence prior to the rx burst and the resulting current consumption note 1: the ldo?s can remain powered up after the initial rx burst . this is to simplify the timi ng for subsequent rx and tx bur sts in traffic mode, as the ldo start up timing is removed along with a power control register access. if the main ldo is powered down after the burst then the described wait time must be obser ved between the de assertion of rx_on and ldo_en. www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pate nts or other rights of third pa rties, which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of mediatek. rev b -11- mediatek proprietary information alert mode wait mode transmit mode 60 50 70 20 30 40 10 transmitter + tx vco synthesizer + lo vco vcxo buffer time vcxo external components fem vcc_ref sen syn_pu lovco_ldo_en ldo_en lovco_corepu active tx burst 200us pa control signals tx_on fem signals ramp 100us dummy i/q signal pll divider power control ma 100 90 80 110 120 i register name power control (addr4) register bits external control signals serial bus AD6548 power control h l h l h l power control figure 10 typical timing of the power up sequence prior to th e tx burst and the resulting current consumption note: this timing diagram assumes a preceding rx burst as shown in fi gure 9, where the ldos are not disabled. this is acceptable for traffic mode. www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pate nts or other rights of third pa rties, which may result from its use. no license is granted by implication or otherwise under an y patent or patent rights of meditek. mediatek proprietary information -12- rev b calibration description the integrated filters and receiver dc offsets must be auto- calibrated to provide optimum ic performance. the calibra- tions are an event that only needs to occurs upon powering up the device. they are initiated by software and can be run con- currently. the calibrations are fully automated and require no further action once initiated. to perform the calibrations : 1) ensure the vcc_ref is applied so that the 26mhz reference oscillator is running. 2) power up and enable the receiver & synthesizer. (the dc_autocal must be low.) 3) wait 50us, for the receiver system to settle. 4) set the st_bb_cal and dc_autocal 1 bits high (in the initialization and set up register). 5) integrated filter calibration will be completed within 1.28ms and the st_bb_cal is automatically cleared by hardware. the filter coefficients produced will be stored in the flt_adj bits. 6) dc offset calibration (for both high and low bands) will be completed in 4.3ms from the start of calibra- tion. 7) once both calibrations are complete the receiver can be powered down; the calibration results are pre- served as long as vdd is present. after calibration the pll and gain settings w ill return to their pre cali- bration values automatically. figure 11 shows the correct power down sequence using two power con- trol writes; the first to turn off the rx_on and circuit blocks, and the second to disable the ldos. note 1: the dc offset calibration is initiated on the rising edge of dc_autocal. during normal operation the dc _autocal should remain high to ensure that the dc offset remains small over all condi- tions. figure 11 show the timing of the initialization and auto calibra- tion sequence, as describe above. sen dc_autocal ldo_en lovco_ldo_en 1.28ms 4.3ms st_bb_cal vcc_ref 50us min lovco_coreenpu syn_pu rx_on init & setup power control power control register name initialization of the remaining registers is possible during this time period power control (addr 4) register bits serial bus AD6548 power control init & setup (addr 0) register bits dc auto calibration time cleared by hardware power control 25us min 1us min figure 11 initialization and auto calibration timing sequence www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pate nts or other rights of third pa rties, which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of mediatek. rev b -13- mediatek proprietary information register definitions register addresses the serial interface word definition provides 5 address bits, gi ving a maximum of 32 words in the protocol. for the AD6548/9 ic not all addresses are allocated. table 5 describes the used addresses. address word length data width main function 0 18 bits 11 bits initialization and setup 1 14 bit 7 bits synthesizer initialization and setup 4 16 bits 9 bits power control 5 13 bits 6 bits agc and lna gain 6 24 bits 17 bits pll divider 29 11 bits 4 bits ic test register 1 31 11 bits 4 bits ic test register 2 register map the bold values are the default values after power-on reset or when the reset bit has been applied bit name description value address 0 d[6..0] initialization and setup initializes AD6548/9. th is register is expected to be programmed mainly at power up. address 0 and opcode d[7] reset resets to the default values (usually zero). the reset bit will be cleared at the following clock edge, normally a part of the next programming word 0: reset is performed 1: no reset is performed d[8] st_bb_cal start baseband & loop filter calibra- tion. calibration will last 1.28 ms. completion clears st_bb_cal. 0: calibration inactive 1: start calibration d[12..9] flt_adj[3..0] baseband and loop filter adjustments. overwritten by baseband cal. 0: highest cut off 0b1111: lowest cut off d[13] dc_autocal positive transition triggers autocal. should stay high to keep autocal re- sults 0: autocal inactive 1: use autocal values d[15..14] ref_op[1..0] reference output mode 0: normal 1: cmos test mode (pll counter o/p) 2 : off 3 : high current d[16] hi_band identifies hi band for use in dc autocal 0: 1800 1: 1900 d[17] low_band identifies lo band for use in dc autocal 0: 850 1: 900 address 1 d[6..0] synthesizer initialization and setup initializes AD6548/9 synthesizer. this register is expected to be programmed mainly at power up. address 1 and opcode d[7] reserved 0 d[13..8] afc_cap[5..0] sets the in ternal caps to coarse tune the crystal frequency (~0.16f steps) 0: min capacitance 63: max capacitance www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pate nts or other rights of third pa rties, which may result from its use. no license is granted by implication or otherwise under an y patent or patent rights of meditek. mediatek proprietary information -14- rev b address 4 d[6..0] power control enables/disables d ifferent sections. this register is expected to be pro- grammed just before and after an active burst address 4 and opcode d[7] lovco_ldo_en enable regulator used for integrated lo vco 0: lo vco ldo disabled 1: lo vco ldo enabled d[8] ldo_en enable ldo regulator used for AD6548/9 rx/tx 0: ldo disabled 1: ldo enabled d[9] rx_on enable receive section . 0: rx section disabled 1: rx section enabled d[10] tx_on enable transmit section 0: tx section disabled 1: tx section enabled d[12..11] b_sel[1..0] band selection . only active with active tx or rx 0: e-gsm 900 selected 1: dcs1800 selected 2: pcs1900 selected 3: gsm850 selected d[13] lovco_corepu enable lo vco power up 0: lo vco disabled 1: lo vco enabled d[14] syn_pu enable synthesizer 0: synthesizer disabled 1: synthesizer enabled d[15] pll_txrx indicate pll word tx or rx 0:rx pll word 1:tx pll word address 5 d[6..0] rf agc and lna gain reduction agc and lna programming. this reg- ister is expected to be programmed one or two times in every receive burst address 5 and opcode d[11..7] gain[4..0] sets the agc gain in 3 db increments 0: 3 db gain 1: 3 db gain 2: 3 db gain 3: 6 db gain 21: 60 db gain d[12] gr reduces the lna gain by 20 db 0: no gain reduction 1: 20 db gain reduction address 6 d[6..0] pll divider programs a new divide word for the pll divider. constructed as a 7 bit integer number [5..127] and an 11 bit fractional number [0..2047] address 6 and opcode d[12..7] int[5..0] integer part(lower 6 bits of 7 bit word- see section 5 pg 9) 0x14 d[23..13] frac[10..0] fractional part 0x000 address 29 d[6..0] test register # 1 test bits address 29 and opcode d[10..7] test bits reserved 0x0 address 31 d[6..0] test register # 2 test bits address 31 and opcode d[10..7] test bits reserved 0x4 (0b0100) table 2 AD6548/9 programming words. www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pate nts or other rights of third pa rties, which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of mediatek. rev b -15- mediatek proprietary information operating conditions specifications parameter symbol min max units battery voltage v bat 2.9 5.5 v crystal oscillator supply vo ltage vcc_ref 2.71 2.79 v serial interface supply voltage v dd 1.6 3.0 v ambient temperature t a ?20 85 c gsm850 transmit band 824 849 mhz e-gsm900 transmit band 880 915 mhz dcs1800 transmit band 1710 1785 mhz pcs1900 transmit band 1850 1910 mhz gsm850 receive band 869 894 mhz e-gsm900 receive band 925 960 mhz dcs1800 receive band 1805 1880 mhz pcs1900 receive band 1930 1990 mhz absolute maximum ratings (t a = +25c unless otherwise stated) v bat to gnd (power down on ly) .....................?0.3v to + 6.0v v bat to gnd powered up ..................................?0. 3v to + 5.5v v dd to gnd ...........................................................?0.3v to 3.3v vcc_ref to gnd.................................................?0.3v to 3.3v digital input voltage to gnd...................... ?0.3v to v dd +0.3v maximum power di ssipation .........................................1000 mw maximum differential input voltage @ lna (rx off)........2 vpk operating temperature range ............................?20 c to +85c storage temperature range.............................. ?60c to +150c maximum junction temp erature tj................................ +110c note: tj=ta+pd*rtheta, rtheta = 25 c/w where pd is the total power dissipation of the chip. th is is dependent on mode (=duty cycle of the various blocks) and battery voltage notes: stresses above those listed under ?absolute maximum ratings? may cau se permanent damage to the device. this is a stress rating only and func- tional operation of the device at these or any other conditions above those listed in the operational sections is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd sensitivity the AD6548/9 is an esd (electrostatic discharge) sensitiv e device. electrostatic charges readily accumulate on the human body and equipment and can discha rge without detection. permanent dama ge may occur to devices subjected to high-energy electrostatic discharges. the AD6548/9 feat ures proprietary esd protection circuitry to dissipate high energy discharges. proper esd pr ecautions are recommended to avoid pe rformance degradation or loss of functionality. unused devices must be st ored in conductive foam or shunts, a nd the foam should be discharged to the destination before devices are removed. warning! esd sensitive device www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwis e agreed to in writing. no responsibility is assumed by mediatek for its use; nor for an y infringements of patents or ot her rights of third parties, wh ich may result from its use. no license is granted by implication or otherwise under any pate nt or patent rights of mediatek. mediatek proprietary information -16- rev b specifications general + regulators operating conditions as above, operating temperature ?20 c to +85 c parameter min typ max units test conditions supply current off 0.05 2 a ldos off vdd not present power down <1 10 a vdd on, ldos disabled wait mode 1.5 ma cload 20pf alert 27 34 ma includes lo vco receive 78 95 ma transmit 120 150 ma regulators ldo1 ground current unloaded 250 a start-up time 50 sec c load 1uf decoupling required for guaranteed stability 0.1 1 uf any esr www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 this information applies to a product under development. its characterist ics and specifications are subject to change without n otice. mediatek assumes no obligation regarding future manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pa tents or other rights of third parties, which may result from its use. no license is gran ted by implication or otherwise under any patent or patent righ ts of mediatek. rev b -17- mediatek proprietary information specifications receive sections operating conditions as above, operating temperature ?20 c to +85 c, input matched parameter min typ max units test conditions / comments gsm850 and e-gsm 900 receiver all specifications are made on the full chain maximum voltage gain gsm 850 83.4 86 88.4 db gr=0 maximum voltage gain e-gsm 900 83.4 86 88.4 db gr=0 temperature coefficient of gain -7 mdb/ c gain reduction 18 20 22 db gr=1 input return loss 12 15 db matched input impedance gsm850 e-gsm 900 24-j51 24-j53 differential dsb noise figure 3.0 4.5 db gr=0 includes baseband contribution gain set to maximum gain input referred 1 db compression point -23 -20 dbm gr=0 gr=1 input ip3 -18 -13 dbm gr=0; baseband gain = 54 db input: ?49 dbm tones @ f_c+800khz and f_c+1600khz input ip 2 38 45 dbm baseband gain = 54 db input ?30dbm tones @ f_c+6000khz and f_c+6070khz: see note i/q gain error 0.5 db quadrature phase error -3 0 3 degrees noise figure degradation in the presence of blocker 3 db -26dbm @ 3mhz ,gr=0, includes syn- thesizer ip2 note (all bands): it can be shown that ip2 performance correlates to am suppression performance. the specified ip2 supports 3gpp ts 45.005 requirements with 0db insertion loss from the antenna to ic pins. additional insertion loss from the antenna improves overall am suppression performance www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwis e agreed to in writing. no responsibility is assumed by mediatek for its use; nor for an y infringements of patents or ot her rights of third parties, wh ich may result from its use. no license is granted by implication or otherwise under any pate nt or patent rights of mediatek. mediatek proprietary information -18- rev b specifications receive section (continued) operating conditions as above, operating temperature ?20 c to +85 c , input matched parameter min typ max units test conditions / comments gsm1800 and gsm1900 receivers all specifications are made on the full chain maximum voltage gain gsm 1800 83.8 86.3 88.8 db gr=0 maximum voltage gain gsm 1900 84.2 86.7 89.2 db gr=0 temperature coefficient of gain -8 mdb/ c gain reduction 18 20 22 db gr=1 input return loss 12 15 db matched input impedance dcs 1800 pcs 1900 8-j26 10-j33 differential dsb noise figure 3.0 4.5 db gr=0 includes baseband contribution gain set to maximum gain input referred 1 db compression point -24 -21 dbm gr=0 gr=1 input ip3 -18 -14 dbm gr=0; baseband gain = 54 db input: ?49 dbm tones @ f_c+800khz and f_c+1600khz input ip 2 36 43 dbm baseband gain = 54 db input ?30dbm tones @ f_c+6000khz and f_c+6070khz: see note i/q gain error 0.4 db quadrature phase error -2.5 2.0 6.5 degrees noise figure degradation in the presence of blocker 4 db -29dbm at 3mhz ,gr=0 ip2 note (all bands): it can be shown that ip2 performance correlates to am suppression performance. the specified ip2 supports 3gpp ts 45.005 requirements with 0db insertion loss from the antenna to ic pins. additional insertion loss from the antenna improves overall am suppression performance www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 this information applies to a product under development. its characterist ics and specifications are subject to change without n otice. mediatek assumes no obligation regarding future manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pa tents or other rights of third parties, which may result from its use. no license is gran ted by implication or otherwise under any patent or patent righ ts of mediatek. rev b -19- mediatek proprietary information specifications receive section (continued) operating conditions as above, operating temperature ?20 c to +85 c parameter min. typ. max. units test conditions / comments baseband amplifiers r load >100 k , c load =47 pf + 5% maximum voltage gain 60 db minimum voltage gain 3 db output 1 db compression point 3 v pp differential, maximum gain gain control range 56 57 58 db gain control resolution 2.5 3 3.5 db gain control linearity 1 db integral linearity baseband filters r load >100 k , c load =47 pf + 5% 3-db cutoff frequency 200 khz all ga in settings, min/max, after filter auto calibration gain flatness 0.5 dbpp dc to 80 khz, min/max differential group delay 0.2 0.3 s dc to 80 khz attenuation template after filter auto calibration @ 200 khz offset 0 3 db @ 400 khz offset 35 db @ 600 khz offset 50 db @ 800 khz offset 60 db @ 1.6 mhz offset 80 db @ 3 mhz offset 90 db @ 6.5 mhz offset 100 db @ >13 mhz offset 100 db output common mode level 1.12 1.22 1. 32 v on i, ib, q, and qb signals output impedance 1.6 k single ended maximum residual dc 300 mv baseband gain 3db to 54db www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwis e agreed to in writing. no responsibility is assumed by mediatek for its use; nor for an y infringements of patents or ot her rights of third parties, wh ich may result from its use. no license is granted by implication or otherwise under any pate nt or patent rights of mediatek. mediatek proprietary information -20- rev b specifications transmit section operating conditions as above, operating temperature ?20 c to +85 c parameter min typ max units test conditions / comments transmitter measured at tx vco output. includes contribution from the synthesizer i and q vin = 1vpp (amplitude of i, ib, q and qb = 0.5vpp). low band modulation template 200khz ?35 ?32 db gsm850/e-gsm900 low band modulation template 250khz ?38 ?35.5 db " " low band modulation template 400khz ?65 ?62 db " " high band modulation template 200khz ?36 ?32 db dcs1800/pcs1900 high band modulation template 250khz ?39 ?35.5 db " " high band modulation template 400khz ?66 ?62 db " " gsm850/egsm phase error 1 2.5 deg(rms) dcs1800/pcs1900 phase error 1 3.0 deg(rms) txop_lo output 1 operating frequency range 824 915 mhz phase noise @ 10mhz -160 -154 dbc/hz phase noise @ 20mhz -166 -164 dbc/hz output power +6 +8 +10 dbm rl=50ohm output vswr <1.5:1 50ohm load pull +/-100 khz open loop, vswr 2:1 all phases output harmonics 2 nd harmonic 3 rd harmonic -20 -10 dbc dbc txop_hi output 1 operating frequency range 1710 1910 mhz phase noise @ 20mhz -162 -156 dbc/hz output power +5 +7 +9 dbm rl=50ohm output vswr <1.5:1 50ohm load pull +/-50 khz open loop, vswr 2:1 all phases output harmonics 2 nd harmonic 3 rd harmonic -20 -10 dbc dbc tx baseband i/q inputs input resistance 30 k each pin , 60k differential input capacitance 3 pf input signal level 0.8 1.0 1.05 vpp meas ured differentially at i or q. common mode input level 1.14 1.2 1.26 v note 1: the txop pins contain a dc voltage and should be ac coupled in the system. www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 this information applies to a product under development. its characterist ics and specifications are subject to change without n otice. mediatek assumes no obligation regarding future manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pa tents or other rights of third parties, which may result from its use. no license is gran ted by implication or otherwise under any patent or patent righ ts of mediatek. rev b -21- mediatek proprietary information specifications fractional-n synthesizer operating conditions as above, operating temperature ?20 c to +85 c unless otherwise noted. parameter min typ max units test conditions synthesizer ssb phase noise at 5khz offset -86 dbc/hz at 400khz offset -122 dbc/hz at 3mhz offset -140 dbc/hz integrated noise (dsb) 2.0 deg(rms) 1khz-1mhz channel spacing 25 khz mod = 1040 (receive mode) 22.2222.. khz mod = 1170 (gsm850/900 transmit mode) 21.05263? khz mod = 1235 (gsm1800/1900 transmit mode) output frequency 2520 2985 mhz lock time 200 s phase error <10 deg synthesizer note: frequency division reduces phase noise contributions at the mixer port by: 9.5db ( rx gsm850/e gsm) 3.5db (rx dcs/pcs) 9.8db (tx gsm850/e gsm) 3.4db (tx dcs/pcs) www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwis e agreed to in writing. no responsibility is assumed by mediatek for its use; nor for an y infringements of patents or ot her rights of third parties, wh ich may result from its use. no license is granted by implication or otherwise under any pate nt or patent rights of mediatek. mediatek proprietary information -22- rev b specifications reference oscillator operating conditions as above, operating temperature ?20 c to +85 c unless otherwise noted. parameter min typ max units test conditions AD6548 crystal oscillator 1 26mhz operation output frequency 26 mhz specified with recommended crystal afc capacitor tuning range +/-20 ppm 25 deg c (63 steps) afc capacitor step size 1.00 1.3 1. 5 ppm around zero ppm operating point varactor tuning range 2 +/-15 ppm 0.2vAD6548/9 reference output output frequency 26 mhz 26mhz crystal output swing 400 600 mvpp max load 20pf duty cycle 45 55 % 50% duty cycle buffer input note 1: specification valid with a suitable crysta l as defined in adi apps note gsm-0109 note 2: after selection of correct afc capacitor va lue at 25 oc as per gsm-0109 apps note. crystal temperature-frequenc y behavior de-embedded www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 this information applies to a product under development. its characterist ics and specifications are subject to change without n otice. mediatek assumes no obligation regarding future manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pa tents or other rights of third parties, which may result from its use. no license is gran ted by implication or otherwise under any patent or patent righ ts of mediatek. rev b -23- mediatek proprietary information serial port specification operating conditions as above, operating temperature ?20 c to +85 c unless otherwise noted. parameter min typ max units test conditions serial interface timing diagram fig 14,15 v ih , input high voltage v dd * 0.7 volts v il , input low voltage v dd * 0.3 volts v oh , output high voltage v dd - 0.2 volts i oh = 100ua v ol , output low voltage 0.2 volts i ol = 100ua static input current ?1 1 a 0< v in < v dd serial data output buffer load 40 pf c in , input capacitance 5 pf timing conditions t clk_w t clk_r serial clock period 38 ns t dst_w t dst_r serial data set up time 8 ns t dhd_w t dhd_r serial data hold time 8 ns t hen_w t hen_r enable set up time to clock high 10 ns t den _w t den _r clock high to enable high 8 ns t dhb_r serial hold on data bus after enable high 5 ns msb lsb t den_w t clk_w t dst_w t dhd_w t hen_w en clk data figure 12 serial interface timing ? write operation www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwis e agreed to in writing. no responsibility is assumed by mediatek for its use; nor for an y infringements of patents or ot her rights of third parties, wh ich may result from its use. no license is granted by implication or otherwise under any pate nt or patent rights of mediatek. mediatek proprietary information -24- rev b ref value description package type / manufacture c1 33nf chip capacitor 0402 murata, rohm , tdk c2 c4 c10 c12 100nf chip capacitor 0402 murata, rohm , tdk c3 220nf chip capacitor 0402 murata, rohm , tdk c5 1nf chip capacitor 0402 murata, rohm , tdk c11 39pf chip capacitor 0402 murata, rohm , tdk c6,c7 4.7pf chip capacitor 1 0402 murata, rohm , tdk c8,c9 8.2pf chip capacitor 1 0402 murata, rohm , tdk l1,l2 5.6nh chip capacitor 1 0402 ceramic multilayer eg toko, or murata, or panasonic, l3,l4 18nh chip capacitor 1 0402 ceramic multilayer eg toko, or murata, or panasonic, l5,l6 1.8nh chip inductor 1 0402 ceramic multilayer eg toko, or murata, or panasonic, l7,l8 2.2nh chip inductor 1 0402 ceramic multilayer eg toko, or murata, or panasonic, z1 850 mhz rx saw chip scale murata or epcos z2 900 mhz rx saw chip scale murata or epcos z3 1800 mhz rx saw chip scale murata or epcos z4 1900 mhz rx saw chip scale murata or epcos x1 26 mhz crystal ndk or toyocm, or kss u1 AD6548 5x5 lfcsp mediatek note 1: matching component: exact will be a ffected by saw specification & pcb layout figure 13 AD6548 typical applications diagram & bill of materials www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 this information applies to a product under development. its characterist ics and specifications are subject to change without n otice. mediatek assumes no obligation regarding future manufacture unless otherwise agreed to in writing. no responsibility is assumed by mediatek for its use; nor for any infringements of pa tents or other rights of third parties, which may result from its use. no license is gran ted by implication or otherwise under any patent or patent righ ts of mediatek. rev b -25- mediatek proprietary information ref value description package type / manufacture c1 33nf chip capacitor 0402 murata, rohm , tdk c2,c12, c14 100nf chip capacitor 0402 murata, rohm , tdk c3 220nf chip capacitor 0402 murata, rohm , tdk c4 15pf chip capacitor 0402 murata, rohm , tdk c13 39pf chip capacitor 0402 murata, rohm , tdk c6,c7 4.7pf chip capacitor 1 0402 murata, rohm , tdk c8,c9 8.2pf chip capacitor 1 0402 murata, rohm , tdk c5,c10,c11 1 nf chip capacitor 0402 murata, rohm , tdk l1,l2 5.6nh chip capacitor 1 0402 ceramic multilayer eg toko, or murata, or panasonic, l3,l4 18nh chip capacitor 1 0402 ceramic multilayer eg toko, or murata, or panasonic, l5,l6 1.8nh chip inductor 1 0402 ceramic multilayer eg toko, or murata, or panasonic, l7,l8 2.2nh chip inductor 1 0402 ceramic multilayer eg toko, or murata, or panasonic, z1 850 mhz rx saw chip scale murata or epcos z2 900 mhz rx saw chip scale murata or epcos z3 1800 mhz rx saw chip scale murata or epcos z4 1900 mhz rx saw chip scale murata or epcos u2 26 mhz vctcxo toyocm, murata,etc. u1 ad6549 5x5 lfcsp mediatek note 1: matching component: exact will be a ffected by saw specification & pcb layout www.datasheet.co.kr datasheet pdf - http://www..net/
AD6548/9 product characteristics and specifications are subject to change without notice. mediatek assumes no obligation regarding futur e manufacture unless otherwis e agreed to in writing. no responsibility is assumed by mediatek for its use; nor for an y infringements of patents or ot her rights of third parties, wh ich may result from its use. no license is granted by implication or otherwise under any pate nt or patent rights of mediatek. mediatek proprietary information -26- rev b figure 14 ad6549 typical applications diagram & bill of materials package dimensions figure 15 package dimensions change list revision chapter title / page description rev b page 1 & 15?????? page 10 note 1 & fig 9?.. page 12 fig 11 & part 7 of text? page 21 (synth note) page 22 reference oscillator spec vdd voltage increased from 2.9 to 3v modified ldo off timing modified ldo off timing corrected band references updated verbiage and added max start-up time www.datasheet.co.kr datasheet pdf - http://www..net/

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